Functional Qualification
If there was a bug in your design, would you be able to find it ?
Certess helps integrated circuit (IC) design teams tackle the most formidable problem in functional verification: the absence of objective quality assurance in the verification of ICs and systems.
Most advanced functional verification teams currently use a combination of techniques to gain visibility into the question of verification quality only to constantly fall short of the ability to truly qualify designs. Although verification engineers have dedicated tools and methodologies for verification quality improvement, functional logic errors still remain the largest causes of chip respins.
We provide engineers with the ability to tell if design errors could go undetected and enable the objective evaluation of the quality of the functional verification, and therefore of the design functionality.
Functional qualification will enable design teams to improve their effectiveness and the predictability of their project schedules, which are currently dominated by the verification task.
Interviews:
Interview with Certess CTO, Mark Hampton
July 13, 2008
http://www.thinkverification.com/
Events:
Next event is CDNLive! On Sep. 9-11 in Silicon Valley.
Info can be found on:
http://www.cadenceevents.com/cdnlive/na/controller.cfm?view=closing.cfp |
