Introducing Functional Qualification

Functional verification is consuming more and more resources in IP design projects. As designs grow in complexity, designers have an increasing need to rely on a dedicated verification team to insure systems fully meet their specifications. The verification team has at its disposal a set of dedicated tools and methodologies for verification automation and quality improvement. However, functional logic errors are the largest cause of re-spins.

This paper describes the fundamental aspects of functional verification that remain invisible to the existing verification tools. It describes in detail functional qualification: a technique that enables design teams to improve their effectiveness and the predictability of project schedules currently dominated by the verification task.

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